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The DFF primitive allows you to program a register as an edge-triggered D flipflop.

To perform functional simulations, you must use the altera_primitives.v library located in the <Quartus II installation directory>edasim_lib directory. For VHDL, you must use the altera_primitives.vhd library located in the <Quartus II installation directory>edasim_lib directory.

DFF <instance_name> (.d(<input_wire>), .clk(<input_wire>),

.clrn(<input_wire>), .prn(<input_wire>), .q(<output_wire>));

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The following VHDL component declaration is located in the= 4 && typeof(BSPSPopupOnMouseOver) 'function') BSPSPopupOnMouseOver(event);'>VHDL Design File (.vhd)ALTERA_PRIMITIVES_COMPONENTS.VHDlocated in the<Quartus II installation directory>librariesvhdlalteradirectory.

COMPONENT DFF

PORT (d : IN STD_LOGIC;

clk : IN STD_LOGIC;

clrn : IN STD_LOGIC;

prn : IN STD_LOGIC;

q : OUT STD_LOGIC );

END COMPONENT;

The VHDL LIBRARY-USE declaration is not required if you use the VHDL Component Declaration.

LIBRARY altera;

USE altera.altera_primitives_components.all;

Inputs				Output
PRN	CLRN	CLK	D	Q
L	H	X	X	H
H	L	X	X	L
L	L	X	X	L
H	H	L	L
H	H	H	H
H	H	L	X	Qo*
H	H	H	X	Qo

* Qo = level of Q before clock pulse

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All flipflops are positive-edge-triggered.

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Note: For information about Quartus II primitive instantiation, go to Using a Quartus II Logic Function.